1. Field of the Invention
This invention relates to a picture storage apparatus and a graphic engine apparatus, such as a display device in a computer graphics system.
2. Description of the Related Art
In a display apparatus employed in a computer graphic system or an engineering workstation, the drawing speed significantly influences the processing capability of the entire system and represents an important factor governing the processing capability. A variety of systems have been developed for elevating the drawing speed. Examples of these systems include a memory interleaving system and a block light system, such as a so-called pixel cache system.
The pixel cache system and the memory interleave system are hereinafter explained.
A display apparatus constructed in accordance with the cache system includes a picture data generator 1 for decoding the commands and generating pixel data, a picture memory 2 having a storage capacity corresponding to the resolution and adapted for storage of pixel data, and a pixel cache memory 3 with a storage capacity of n.times.n pixels placed between the pixel data generator 1 and the picture memory 2 and as shown in FIG. 1.
The commands supplied from a computer, such as commands for drawing a line or a surface, data transfer command in the picture memory, such as so-called BITBLT (Bit Block Transfer) command, or a fill command of filling the inside of a figure, are decoded by picture data generator 1 to generate pixel data. These pixel data are stored in a picture memory 2 via high-speed pixel cache memory 3 and pixel data stored in the picture memory 2 are read out in timed relation to the scanning by a Braun tube, not shown, by a raster scanning, for displaying a picture. That is, high-speed drawing is enabled by arranging the pixel cache memory 3, which permits of high speed accessing, between the picture data generator 1 and the picture memory 2. For example, if moving, copying or filling of a small figure can be made within the pixel cache memory 3 by e.g. a transfer command or a fill command, reading of pixel data from pixel memory 2 may be eliminated to raise the drawing speed.
However, with the pixel cache system, if the pixel cache memory 3 is of a small storage capacity and addresses indicating the positions of the pixel data from pixel data generator 1 on the display screen exceeds boundary of the address region of the pixel data stored by the pixel cache memory 3, it becomes necessary to read and write pixel data between the pixel cache memory 3 and the picture memory 2 whenever the addresses traverse the boundary of the address region. Above all, the processing efficiency is significantly lowered when the picture memory 2 is random accessed to update pixel data.
The display apparatus constructed in accordance with the memory interleave system includes a picture data generator 5 for decoding commands and generating pixel data, an n number of memories m.sub.i, where i=0.about.n-1, having a storage capacity equal to 1/n corresponding to the resolution of the display screen and adapted for storing the pixel data, and an n number of memory controllers MP.sub.i m where i=0.about.n-1, for controlling the n number of memories m.sub.i.
The n number of memories m.sub.i make up a picture memory 6 corresponding to the display screen, with the memories m.sub.i dividing the picture memory 6 into e.g. 16 parts (N=16), as shown in FIG. 3. If the pixel at the upper left corner on the display screen is an origin, the horizontal and vertical directions are x and y axes, and the pixels on the display screen are indicated by P.sub.x, y, where x, y are coordinates or pixel addresses on the display screen, the memories m.sub.0, m.sub.1, m.sub.2, m.sub.3, m.sub.4, m.sub.5 . . . m.sub.15 store pixel data of the pixels P.sub.4q,4r, P.sub.4q+1,4r, P.sub.4q+2,4r, P.sub.4q+3,4r, pixels P.sub.4q,4r+1, P.sub.4q+1,4r+1, . . . P.sub.4q+3,4r+3 (q, r=0, 1, 2, . . . ).
For example, commands for drawing line segments or pictures from CPU, data transfer commands or fill commands are decoded by picture data generator 5 to generate pixel data which are stored in the memories m.sub.i based on addresses supplied commonly from pixel data generator 5 under control by memory controller MP.sub.i. The stored pixel data in the memories M.sub.i are read out by raster scanning for displaying the picture on the Braun tube, not shown. That is, 16 memory controllers MP.sub.0 .about.MP.sub.15 access one of blocks B.sub.x, y constituted by 4.times.4 pixels P.sub.4q,4r .about.P.sub.4q+3,4r+3 based on block addresses (X, Y) (X, Y=0, 1, 2, . . . ) supplied from picture data generator 5, for simultaneously accessing the 16 pixels in the block B.sub.x, y to realize a high processing rate, as shown in FIG. 17.
However, this memory interleave system has a drawback that, if the pixel addresses (x, y) indicating the positions on the display screen exceed the boundary of the block B.sub.x, y, the processing efficiency is lowered significantly. Besides, when accessing is had continuously to the pixels P.sub.x, y supervised by the same memory controller MP.sub.i, the processing efficiency is similarly lowered significantly.
Taking an example of a data transfer command,such as BITBLT command, if pixel data of an arbitrary block B.sub.x, y of picture memory 6, for example block B.sub.0,2, is to be transferred to block B.sub.2,1, as shown by the uppermost double-line arrow, the pixel data read out based on the block address (0, 2) from pixel data generator 5 are written by the block address (2, 1 ) under control by each memory controller MP.sub.i, as shown in FIG. 17. In this manner, data transfer may be achieved within the memory m.sub.i control led by the memory controller MP.sub.i itself to realize high-speed data transfer. However, if the area of the originate or the area of the receiver are not coincident with the boundary of the block B.sub.x, y, that is, if pixel data of block B.sub.0, 2 are to be transferred, as shown by the lowermost double-line arrow, to an area 7 composed of 4.times.4 pixels P.sub.x, y, as shown in FIG. 3, each memory controller MP.sub.i is unable to transfer data within the memory m.sub.i controlled by memory controller MP.sub.i, so that data transfer cannot be achieved without communication between the memory controllers MP.sub.i .
Consequently, if data transfer is to be effected in the above-described manner, it is necessary to effect communication, such as data transfer, between memory controllers MP.sub.i, and subsequently to write pixel data four times into blocks B.sub.1,2, B.sub.2,2, B.sub.1,3 and B.sub.2,3 present in the area 7, thus lowering the processing efficiency.
With the above-described memory interleave system, which consists in dividing the picture memory 82 having the storage capacity conforming to the resolution of the display screen into an n number of sections and controlling the memories m.sub.i by dedicated memory controllers MP.sub.i for simultaneously accessing 16 pixels P.sub.x, y in the same block B.sub.x, y to achieve high processing speed, the memory controller MP.sub.i has no address generating function, as a result of which the processing efficiency tends to be lowered significantly.